An expandable column fft architecture using circuit switching networks

The Fast Fourier Transform (FFT) is widely used in various digital signal processing applications. The performance requirements for FFT in modern real-time applications has increased dramatically due to the high demand on capacity and performance of modern telecommunication systems, where FFT plays a major role. Software implementations of FFT running on a general purpose computer can no longer meet current speed requirements. However, recent advances in VLSI technology have made it possible to implement the entire FFT system on a single silicon substrate. This paper presents a column FFT design suitable for ULSI (Ultra Large Scale Integration) implementations. The basic building block is a 64-point column FFT. FFTs with longer transform lengths can be easily realized using the 64-point column FFT building block. The butterry processors in the column FFT are connected using circuit switching networks. The circuit switching networks not only provide dynamically reconngurable in-terconnections among the butterry processors, but also provide a fault-tolerant 1 capability. Bit-serial arithmetic is used in the architecture. Assuming the data wordlength is 16 bits, the 1024-point column FFT engine proposed in this paper is capable of processing 1024 complex data samples in 533 clock cycles. If the clock frequency is 40MHz, it will take 13.3 s to complete a 1024-point FFT.